for pricing delivery, and ordering information please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. general description the max9320/max9320a are low-skew, 1-to-2 differen- tial drivers designed for clock and data distribution. the input is reproduced at two differential outputs. the dif- ferential input can be adapted to accept single-ended inputs by applying an external reference voltage. the max9320/max9320a feature ultra-low propagation delay (208ps), part-to-part skew (20ps), and output-to- output skew (6ps) with 30ma maximum supply current, making these devices ideal for clock distribution. for interfacing to differential hstl and lvpecl signals, these devices operate over a +2.25v to +3.8v supply range, allowing high-performance clock or data distrib- ution in systems with a nominal +2.5v or +3.3v supply. for differential lvecl operation, these devices operate from a -2.25v to -3.8v supply. the pinout is the only difference between the max9320 and max9320a. multiple pinouts are provided to simplify routing across a backplane to either side of a double- sided board. these devices are offered in space-saving 8-pin sot23, ?ax, and so packages. applications precision clock distribution low-jitter data repeater protection switching features ? improved second source of the mc10lvep11 (max9320) ? +2.25v to +3.8v differential hstl/lvpecl operation ? -2.25v to -3.8v lvecl operation ? low 22ma (typ) supply current ? 20ps (typ) part-to-part skew ? 6ps (typ) output-to-output skew ? 208ps (typ) propagation delay ? minimum 300mv output at 3ghz ? outputs low for open input ? esd protection >2kv (human body model) ? available in thermally enhanced exposed-pad so package max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers ________________________________________________________________ maxim integrated products 1 6 sot23 d v cc d 1 2 3 4 8 q1 5 q1 7 q0 v ee q0 max9320a 60k ? 100k ? 100k ? 100k ? 60k ? 100k ? v cc v ee 6 max/so q0 q1 1 2 3 4 8 d 5 v ee 7 d v cc max9320 q1 q0 6 sot23 d v cc d 1 2 3 4 8 q1 5 q1 7 q0 v ee q0 max9320 60k ? 100k ? 100k ? v cc v ee pin configurations 19-2201; rev 3; 11/04 ordering information part temp range pin- package top mark max9320 eka-t -40? to +85? 8 sot23-8 aalj max9320esa -40? to +85? 8 so max9320xesa -40? to +85? 8 so-ep* max9320eua -40? to +85? 8 ?ax max9320a eka-t -40? to +85? 8 sot23-8 aaiw * contact factory for availability.
max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers 2 _______________________________________________________________________________________ absolute maximum ratings dc electrical characteristics (v cc - v ee = +2.25v to +3.8v, outputs loaded with 50 ? ?% to v cc - 2v. typical values are at v cc - v ee = +3.3v, v ihd = v cc - 1.0v, v ild = v cc - 1.5v, unless otherwise noted.) (notes 1, 2, 3) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to v ee ..........................................................................+4.1v d or d .................................................. v ee - 0.3v to v cc + 0.3v d to d .................................................................................?.0v continuous output current .................................................50ma surge output current........................................................100ma junction-to-ambient thermal resistance in still air 8-pin sot23.............................................................+112?/w 8-pin ?ax ..............................................................+221?/w 8-pin so...................................................................+170?/w junction-to-ambient thermal resistance with 500 lfpm airflow 8-pin sot23...............................................................+78?/w 8-pin ?ax ..............................................................+155?/w 8-pin so.....................................................................+99?/w junction-to-case thermal resistance 8-pin sot23...............................................................+80?/w 8-pin ?ax ................................................................+39?/w 8-pin so.....................................................................+40?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? esd protection human body model (d, d , q_, q_ ) .................................>2kv soldering temperature (10s) ...........................................+300? -40 c +25 c +85 c parameter sym bo l conditions min typ max min typ max min typ max units differential input (d, d ) high voltage of differential input v ihd v ee + 1.2 v cc v ee + 1.2 v cc v ee + 1.2 v cc v low voltage of differential input v ild v ee v cc - 0.1 v ee v cc - 0.1 v ee v cc - 0.1 v for v cc - v ee < +3.0v 0.1 v cc - v ee 0.1 v cc - v ee 0.1 v cc - v ee differential input voltage v ihd - v ild for v cc - v ee +3.0v 0.1 3.0 0.1 3.0 0.1 3.0 v input high current i ih 150 150 150 ? d input low current i ild -10 100 -10 100 -10 100 ? d input low current i il d -150 +150 -150 +150 -150 +150 ? differential outputs (q_, q_ ) single-ended output high voltage v oh figure 1 v cc - 1.135 v cc - 0.885 v cc - 1.07 v cc - 0.82 v cc - 1.01 v cc - 0.76 v
max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 3 dc electrical characteristics (continued) (v cc - v ee = +2.25v to +3.8v, outputs loaded with 50 ? ?% to v cc - 2v. typical values are at v cc - v ee = +3.3v, v ihd = v cc - 1.0v, v ild = v cc - 1.5v, unless otherwise noted.) (notes 1, 2, 3) ac electrical characteristics (v cc - v ee = +2.25v to +3.8v, outputs loaded with 50 ? ?% to v cc - 2v, input frequency = 1.5ghz, input transition time = 125ps (20% to 80%), v ihd = v ee + 1.2v to v cc , v ild = v ee to v cc - 0.15v, v ihd - v ild = 0.15v to the smaller of 3v or v cc - v ee . typical values are at v cc - v ee = +3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, unless otherwise noted.) (note 5) -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units single-ended output low voltage v ol figure 1 v cc - 1.935 v cc - 1.685 v cc - 1.87 v cc - 1.62 v cc - 1.81 v cc - 1.56 v differential output voltage v oh - v ol figure 1 550 550 550 mv power supply supply current i ee (note 4) 20 28 22 28 23 30 ma -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units differential input-to- output delay t plhd , t phld figure 1 145 203 265 155 208 265 160 220 270 ps output-to- output skew t skoo (note 6) 6 30 6 30 6 30 ps part-to-part skew t skpp (note 7) 20 120 20 110 20 110 ps f in = 1.5ghz, clock pattern 1.7 2.8 1.7 2.8 1.7 2.8 added random jitter (note 8) t rj f in = 3.0ghz, clock pattern 0.6 1.5 0.6 1.5 0.6 1.5 ps (rms) added deterministic jitter t dj 3.0gbps 2 23 -1 prbs pattern (note 8) 57 80 57 80 57 80 ps (p-p)
note 1: measurements are made with the device in thermal equilibrium. note 2: current into a pin is defined as positive. current out of a pin is defined as negative. note 3: dc parameters production tested at t a = +25 c. guaranteed by design and characterization over the full operating temper- ature range. note 4: all pins open except v cc and v ee . note 5: guaranteed by design and characterization. limits are set at ? sigma. note 6: measured between outputs of the same part at the signal crossing points for a same-edge transition. note 7: measured between outputs of different parts at the signal crossing points under identical conditions for a same-edge transition. note 8: device jitter added to the input signal. max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers 4 _______________________________________________________________________________________ -40 c +25 c +85 c parameter symbol conditions min typ max min typ max min typ max units v oh - v ol 300mv, clock pattern, figure 1 3.0 3.0 3.0 switching frequency f max v oh - v ol 550mv, clock pattern, figure 1 2.0 2.0 2.0 ghz output rise/fall time (20% to 80%) t r , t f figure 1 50 88 120 50 89 120 50 90 120 ps ac electrical characteristics (continued) (v cc - v ee = +2.25v to +3.8v, outputs loaded with 50 ? ?% to v cc - 2v, input frequency = 1.5ghz, input transition time = 125ps (20% to 80%), v ihd = v ee + 1.2v to v cc , v ild = v ee to v cc - 0.15v, v ihd - v ild = 0.15v to the smaller of 3v or v cc - v ee . typical values are at v cc - v ee = +3.3v, v ihd = v cc - 1v, v ild = v cc - 1.5v, unless otherwise noted.) (note 5)
max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 5 35 10 -15 -40 60 85 supply current, i ee vs. temperature max9320 toc01 temperature ( c) supply current (ma) 16 17 18 19 20 21 15 24 23 25 22 500 2500 2000 1500 1000 0 3000 3500 output amplitude, v oh - v ol vs. frequency max9320 toc02 frequency (mhz) output amplitude (v) 0.1 0.2 0.3 0.4 0.5 0 0.8 0.7 0.9 0.6 10 -15 -40 60 35 85 transition time vs. temperature max9320 toc03 temperature ( c) transition time (ps) 86 87 88 85 90 91 89 t r t f 1.4 1.0 3.4 3.0 2.6 2.2 1.8 3.8 propagation delay vs. high voltage of differential input, v ihd max9320 toc04 v ihd (v) propagation delay (ps) 200 205 210 195 220 225 215 t plhd t phld v ihd - v ild = 0.5v 10 -15 -40 60 35 85 propagation delay vs. temperature max9320 toc05 temperature ( c) propagation delay (ps) 170 180 190 200 210 160 230 240 220 t plhd t phld t ypical operating characteristics (v cc = +3.3v, v ee = 0, input transition time = 125ps (20% to 80%), v ihd = v cc - 1v, v ild = v cc - 1.5v, f in = 1.5ghz, outputs loaded with 50 ? to v cc - 2v, t a = +25?, unless otherwise noted.)
max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers 6 _______________________________________________________________________________________ pin description (max9320) pin description (max9320a) pin max/so sot23 name function 18 q0 noninverting q0 output. typically terminate with 50 ? resistor to v cc - 2v. 27 q0 inverting q0 output. typically terminate with 50 ? resistor to v cc - 2v. 36 q1 noninverting q1 output. typically terminate with 50 ? resistor to v cc - 2v. 45 q1 inverting q1 output. typically terminate with 50 ? resistor to v cc - 2v. 52v ee negative supply voltage 64 d inverting differential input. 60k ? pullup to v cc and 100k ? pulldown to v ee . 73 d noninverting differential input. 100k ? pulldown to v ee . 81v cc positive supply voltage. bypass from v cc to v ee with 0.1? and 0.01? ceramic capacitors. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. pin sot23 name function 1v cc positive supply voltage. bypass from v cc to v ee with 0.1? and 0.01? ceramic capacitors. place the capacitors as close to the device as possible with the smaller value capacitor closest to the device. 2v ee negative supply voltage 3 d inverting differential input. 60k ? pullup to v cc and 100k ? pulldown to v ee . 4d noninverting differential input. 100k ? pulldown to v ee . 5 q1 inverting q1 output. typically terminate with 50 ? resistor to v cc - 2v. 6q 1 noninverting q1 output. typically terminate with 50 ? resistor to v cc - 2v. 7 q0 inverting q0 output. typically terminate with 50 ? resistor to v cc - 2v. 8q 0 noninverting q0 output. typically terminate with 50 ? resistor to v cc - 2v.
max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 7 detailed description the max9320/max9320a low-skew, 1-to-2 differential drivers are designed for clock and data distribution. for interfacing to differential hstl and lvpecl signals, these devices operate over a +2.25v to +3.8v supply range, allowing high-performance clock and data distri- bution in systems with a nominal +2.5v or +3.3v sup- ply. for differential lvecl operation, these devices operate from a -2.25v to -3.8v supply. inputs the maximum magnitude of the differential input from d to d is v cc - v ee or 3.0v, whichever is less. this limit also applies to the difference between any reference voltage input and a single-ended input. the differential inputs have bias resistors that drive the outputs to a differential low when the inputs are open. the inverting input, d , is biased with a 60k ? pullup to v cc and a 100k ? pulldown to v ee . the noninverting input, d, is biased with a 100k ? pulldown to v ee . specifications for the high and low voltages of the dif- ferential input (v ihd and v ild ) and the differential input voltage (v ihd - v ild ) apply simultaneously (v ild cannot be higher than v ihd ). outputs output levels are referenced to v cc and are consid- ered lvpecl or lvecl, depending on the level of the v cc supply. with v cc connected to a positive supply and v ee connected to gnd, the outputs are lvpecl. the outputs are lvecl when v cc is connected to gnd and v ee is connected to a negative supply. a single-ended input of ?00mv around a reference voltage or a differential input of at least ?00mv switch- es the outputs to the v oh and v ol levels specified in the dc electrical characteristics table. applications information supply bypassing bypass v cc to v ee with high-frequency surface-mount ceramic 0.1? and 0.01? capacitors in parallel as close to the device as possible, with the 0.01? value capacitor closest to the device. use multiple parallel vias for low inductance. traces input and output trace characteristics affect the perfor- mance of the max9320/max9320a. connect each signal of a differential input or output to a 50 ? charac- teristic impedance trace. minimize the number of vias to prevent impedance discontinuities. reduce reflec- tions by maintaining the 50 ? characteristic impedance through connectors and across cables. reduce skew within a differential pair by matching the electrical length of the traces. the exposed-pad (ep) so package can be soldered to the pc board for enhanced thermal performance. if the ep is not soldered to the pc board, the thermal resis- tance is the same as the regular so package. the ep is connected to the chip v ee supply. be sure that the pad does not touch signal lines or other supplies. contact the maxim packaging department for guide- lines on the use of ep packages. output termination terminate outputs through 50 ? to v cc - 2v or use an equivalent thevenin termination. terminate both out- puts and use the same termination on each for the low- est output-to-output skew. when a single-ended signal is taken from a differential output, terminate both out- puts. for example, if q0 is used as a single-ended out- put, terminate both q0 and q0. chip information transistor count: 182 figure 1. differential transition time and propagation delay timing diagram 0 (differential) 80% 20% 80% 20% 0 (differential) v oh - v ol v ihd - v ild v ihd v ild v oh v ol q_ q t plhd t phld t r t f d d (q_) - (q_)
sot23, 8l .eps rev. document control no. approval proprietary information title: 3.00 2.60 e c e1 e between 0.08mm and 0.15mm from lead tip. 8. meets jedec mo178. 8 0.60 1.75 0.30 l2 0 e1 e l 1.50 e1 0.65 bsc. 1.95 ref. 0.25 bsc. gauge plane seating plane c c l pin 1 i.d. dot (see note 6) l c l c a2 e1 d detail "a" 5. coplanarity 4 mils. max. note: 7. solder thickness measured at flat section of lead 6. pin 1 i.d. dot is 0.3 mm ? min. located above pin 1. 4. package outline inclusive of solder plating. 3. package outline exclusive of mold flash & metal burr. heel of the lead parallel to seating plane c. 2. foot length measured from lead tip to upper radius of 1. all dimensions are in millimeters. l2 l a1 a 0.45 1.30 0.15 1.45 max 0.28 b 0.90 a2 0.00 a1 0.90 a min symbol 3.00 0.20 2.80 d 0.09 c see detail "a" l c b e d 1 21-0078 1 package outline, sot-23, 8l body 0 0 max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers 8 _______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers _______________________________________________________________________________________ 9 8l, soic exp. pad.eps b 1 1 21-0111 package outline 8l soic, .150" exposed pad package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
max9320/max9320a 1:2 differential lvpecl/lvecl/hstl clock and data drivers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) soicn .eps package outline, .150" soic 1 1 21-0041 b rev. document control no. approval proprietary information title: top view front view max 0.010 0.069 0.019 0.157 0.010 inches 0.150 0.007 e c dim 0.014 0.004 b a1 min 0.053 a 0.19 3.80 4.00 0.25 millimeters 0.10 0.35 1.35 min 0.49 0.25 max 1.75 0.050 0.016 l 0.40 1.27 0.394 0.386 d d min dim d inches max 9.80 10.00 millimeters min max 16 ac 0.337 0.344 ab 8.75 8.55 14 0.189 0.197 aa 5.00 4.80 8 n ms012 n side view h 0.244 0.228 5.80 6.20 e 0.050 bsc 1.27 bsc c h e e b a1 a d 0 -8 l 1 variations:
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